Once the signal VREQn is set, the voltage of the subsystem CPU or DSP need not be adjusted by the software again and again. In comparison to the previous software design, it firstly strengthens the accuracy of voltage and frequency estimation. Secondly, it lightens the load of CPU timing tracking in a way. Figure 9The DVFS structure.In the progress of the DVFS, the SPCU can accurately predict the voltage that is needed in the next period of time according to the current CPU idle time, which supports two scaling steps (down, up). Each CPU of the three subsystems can be separately configured with the scaling down threshold value (T1) and the scaling up threshold value (T2). It is worth emphasizing that the two threshold values of the CPU idle time have to be set before the DVFS is requested. In the meantime, the moving average algorithm (MAA) is firstly adopted in the DVFS. The MAA not only tracks and samples the idle time of the every CPU with small enough intervals but also executes the accumulation and average calculation of the idle times. The MAA formula is given as follows:Tup(n+1)=1N��k=0N?1T(n?k),Tdown(n+1)=1M��k=0M?1T(n?k),(8)where n, M, and N are the positive integers and usually M > N > 0. Tup(n + 1) stands for the average of the idle time from the sampling timing 0 to N ? 1, Tdown(n + 1) stands for the average of the idle time from the sampling timing 0 to M ? 1. Based on (8), the voltage and clock of CPU scaling down step condition is fulfilled if Tdown(n + 1) > T1. Similarly, the voltage and clock of CPU scaling up step condition is fulfilled if Tup(n + 1) < T2. Figure 10 shows the specific automatic transition for the DVFS. Figure 10The intelligent transition for DVFS.The DVFS has its own timer that can be set to the expected maximum voltage settling time. For example, if a voltage ramping slew rate of 5mV per microsecond is used in changing to the adjacent voltage, it only takes 40 microseconds to stabilize from VLow (0.8V) to VMedium (1.0V). Whenever the voltage scaling timer elapses, an interrupt can be triggered. As shown in Table 2, it is obvious that the power consumption of each CPU is reduced with the DVFS in the actual test. Furthermore, compared with conventional software way (CSW) [29�C31], the hardware DVFS has the absolute advantage in saving energy. Thus, we can clearly get a conclusion that the hardware DVFS is an efficient and smart way to save power. In Future, the hardware DVFS will be dominant in the OWCS because of the high efficiency. Table 2Saving power with the DVFS.9. The Aging MonitorIt is meaningful for designers to analyze the important aging data so as to optimize the power system of OWCS. But in the conventional OWCS, the aging monitor has never been used successfully because of its implement complexity [31].